Effective Vcc TO Vss power ESD protection device

ABSTRACT

A novel device and process is described for an ESD protection device for ESD voltages appearing on IC power voltage bus lines. The invention consists of an ESD protection discharging NMOS with source connected to a first voltage bus line, or Vcc, and having the drain connected to a second voltage bus line, or ground. The NMOS device gate is connected to ground through a diffused resistor assuring the device remains in an off state during normal operation. An unique aspect of the invention is a special diffusion under and around the device drain which lowers the drain to substrate breakdown voltage enabling the ESD protection current discharge to start at a lower voltage than otherwise. This feature reduces voltage stress on the gates of active devices being protected, and enables higher ESD current discharges at the same power level as for devices without the special drain diffusion.

BACKGROUND OF THE INVENTION

[0001] (1) Field of the Invention

[0002] The present invention relates generally to a structure of andmanufacturing process for a semiconductor device which provides improvedESD protection of active semiconductor devices and more particularly toa Vcc to Vss protection element for complimentary metal oxidesemiconductor (CMOS) circuit configuration.

[0003] (2) Description of Prior Art

[0004] Because of high input impedance and thin oxide gate structures,the problem of Electrostatic Discharge (ESD) damage with field effecttransistor (FET) devices can be severe. Therefore the input/output (I/O)circuit locations or pads usually have a protective device connectedbetween the I/O pad and the internal circuits which allows the ESDcurrent to be shunted to ground. Another important characteristic of theESD protection device is that it must not interfere with the operationof the devices it is designed to protect, while at the same timeproviding good protection when abnormal or ESD voltage incidents occur.

[0005] A representative logic circuit with prior art ESD protection forthe I/O logic circuitry is shown in FIG. 1A. Section 4 in FIG. 1A showsthe logic output pre-driver section, with outputs IN1 and IN2 feedingthe driver and internal logic ESD protection string 6. N1 feeds the gateof used P channel metal oxide semiconductor (PMOS) PU1 which is on forlow IN1 signals presenting a high voltage of approximately Vcc at theI/O pad 8. Output IN2 feeds the gate of a N channel metal oxidesemiconductor (NMOS) NU2 which, when N2 is high, is on presenting a lowvoltage to I/O pad 8.

[0006] The typical logic, I/O ESD protection device consists of a NMOSNU1 with the drain connected to the I/O pad 8. A parasitic NPN bipolardevice, not shown in FIG. 1A, is essentially in parallel with the NMOSdevice and has a collector base junction breakdown triggered by the ESDvoltage. A P− dopent region 28 beneath the N+ drain region has theeffect of reducing the collector base junction breakdown voltage. Oncetriggered by an ESD incident, the parasitic device operates in asecondary breakdown mode to clamp the ESD voltage to a suitable leveland pass the high current to a second voltage source Vss, typicallyground. Section 7 in FIG. 1A represents a conventional Vcc to Vss ESDNMOS protection device without any special diffusions in its elements.

[0007] A typical N channel logic and I/O FET protection device crosssection is depicted in FIG. 1B. An N-channel FET is situated on aP-substrate 10. The device consists of field oxide isolation (FOX)regions 12, a gate structure consisting of a conducting element 16typically polysilicon, with a gate insulation oxide 14, and oxidespacers 18. The gate and FOX are shown covered with an insulation layer20, typically silicon oxide (SiO₂) or borophosphosilicate glass (BPSG).Not depicted for clarity are the electrical contact and conductordetails. The source 22 and drain 24 elements consist of lightly doped Nregions (LDD) 26 and heavily doped N+ regions for source 22 and drain24. Incorporated beneath the N+ drain region 24 is a P− region 28 whichis typically created by implanting boron through the pre-metal contactopenings.

[0008] The P dopent concentration in the P− area 28 is higher than thatin the substrate in general. Junction breakdown is inverselyproportional to the impurity concentration. Therefore, the P− regionlowers the drain to substrate junction breakdown voltage by increasingthe substrate impurity concentration at the junction boundary. Thiseffect enhances the ESD protection of the device. Note that the P−region 28 in prior art is contained near the center of the drain region24 in a region smaller than the drain region 24 and does not approachthe drain areas near the edge of the gate.

[0009] In addition to the specific diffusion design of the conventionalESD protection device, the conventional prior art device is placed toprotect ESD events with respect to the I/O pad.

[0010] Often overlooked is the need for improved ESD protection betweenthe power buses, typically called Vcc and Vss. ESD voltages and energycan be coupled to the Vss bus, and can cause high channel current fordevices in the “on” state as well as cause high gate stresses fordevices in electrical proximity to the Vss bus. The result isdegradation in overall IC chip and circuit ESD protection performance.

[0011] The invention describes a method and ESD IC power bus protectiondevice with enhanced ESD protection capability.

[0012] The following patents describe ESD protection devices.

[0013] U.S. Pat. No. 5,898,205 (Lee) describes an ESD protection circuitusing NMOS and PMOS devices.

[0014] U.S. Pat. No. 5,953,601 (Shiue et al.) discloses an ESDimplantation step using boron. The ion implantation is spaced from thepolysilicon gate.

[0015] U.S. Pat. No. 5,929,493 (Wu) teaches a CMOS process usingblanket, low dose boron implant to adjust with for ESD protectiondevices.

[0016] U.S. Pat. No. 5,559,352 (Hsue et al.) discloses a method toimprove an ESD protection device using ion implantation. Theimplantation is spaced from the polysilicon gate.

SUMMARY OF THE INVENTION

[0017] Accordingly, it is the primary objective of the invention toprovide a novel, effective device structure, and a device developmentmethod, for protecting integrated circuits from damage caused by ESDevents occurring during circuit operation, in particular for ESD eventsbetween Vcc and Vss power lines.

[0018] In addition, it is an objective of this invention to provide thisESD protection while maintaining appropriate normal circuit operatingparameters of the devices being protected.

[0019] It is yet another object of the invention to provide a processmethod for forming the ESD protection structure that is fully compatiblewith the manufacturing process of the devices being protected.

[0020] The above objectives are achieved in accordance with theembodiments of the invention that describes a process and novelstructure for a ESD protection NMOS FET device for the integratedcircuit (IC) power bus elements, typically known as Vcc and Vss. A NMOSFET device is created between the Vcc and Vss power buses with thesource connected directly to Vss, or ground. The device gate isconnected to Vss through a resistor and the device drain is connected toVcc.

[0021] A particularly unique feature of the invention is an acceptorspecie implant, typically boron, into the device drain region. Thisimplant produces a P− region around and below the N+ device drain andextends into proximity of, or has a small overlap with the gate channelarea. As previously noted, the junction breakdown voltage is inverselyproportional to the doping levels at the junction boundary region. Thespecial acceptor implant produces a N− region of higher concentrationthan the substrate, and hence reduces the breakdown voltage of the P-Njunction. This allows for a higher ESD discharge current for a givenpower, since power is a product of current times voltage. Since thedevice is placed between the voltage buses, junction capacitance is notas critical a factor as it is for the active logic circuits.

[0022] A NPN parasitic bipolar transistor exists in parallel with theNMOS device, with the collector formed with the NMOS drain, the P baseformed by the P substrate, and the collector formed with the NMOS drain.A high voltage from an ESD event on the Vcc power bus causes the PNcollector junction to breakdown, raising the substrate voltage providingpositive base voltage further enhancing turn on of the parasitic NPNtransistor causing the ESD current to be shunted to Vss preventingdamage to the active devices. In addition, if the ESD energy issufficient, hot carrier tunneling will occur causing a positive voltageto appear on the NFET gate also turning on that device shuntingadditional ESD current to Vss.

[0023] The gate of the NMOS ESD device is connected to Vss or groundthrough a resistor, assuring that the device is in the off state duringnormal circuit operation and therefore it does not impact normal circuitoperation.

BRIEF DESCRIPTION OF THE DRAWINGS

[0024]FIG. 1A is a schematic of prior art I/O string ESD protectiondevice.

[0025]FIG. 1B is a cross section representation of a conventional priorart NMOS ESD logic protection device showing a limited implant ofopposite dopent under the drain region of the logic protection device.

[0026]FIG. 2A is a schematic representation of the invention showing the“used” I/O string and the “dummy” I/O string, with a unique NMOS ESD busprotection device with special drain implant.

[0027]FIG. 2 is a cross section of the NMOS bus ESD protection devicewith special drain implant.

[0028]FIG. 3 is a flow diagram of the method of developing the specialNMOS ESD protection circuit for stacked NMOS ESD power bus protection.

DESCRIPTION OF THE PREFERRED EMBODIMENTS

[0029]FIG. 2 shows in schematic form the invention as embodied by acascaded complimentary CMOS circuit string. The first string is the“used” or active string. It consists of a PMOS PU1 with the sourceconnected to Vcc, a voltage typically between 2.5 and 5.0 volts, and thegate connected to an internal logic signal line IN1.

[0030] The drain is connected to the I/O pad 100 and to the drain of thecascaded first “used” NMOS NU1. The cascaded NMOS NU1 has its gate tiedto Vcc and the source connected to the drain of the second “used” NMOSNU2. The source of NMOS NU2 is connected to ground while the gate isconnected to a internal logic signal line IN2. The number of activestrings is not limited to only one series connected complimentarycascaded string. The output current is a function of string currentdrive capability and the number of “used” or active strings in parallelconnected to the same output pad. It is estimated that each activeoutput string can supply between 2 and 48 milliamperes (ma) of outputcurrent.

[0031] In parallel with the “used” active string is an unused or dummystring consisting of a PMOS PD1 with gate and source connected to Vcc,and drain connected to the I/O pad 100, and the cascaded NMOS ND1 drain.The gate of cascaded NMOS ND1 is connected to Vcc and the source isconnected to the drain of NMOS ND2. The gate and source of the secondNMOS ND2 are connected to ground.

[0032] During normal circuit operation, a high logic signal from theinternal circuits will turn on the device NMOS NU2, essentially pullingdown the voltage at the I/O pad 100 to ground, as the cascade deviceNMOS NU1 with the gate tied to Vcc is essentially always on.

[0033] Also, with the logic signal line high, “used” PMOS PU1 is turnedoff, assuring no current will flow except during the switching cycle.

[0034] Conversely, when the internal logic signal is low, NMOS deviceNU2 will be turned off and PMOS device PU1 will be turned on, providinga voltage at or near Vcc to be placed on the output pad 100. Again,current will only flow during the switching cycle.

[0035] Power bus ESD protection NMOS device NP1 is a key feature of theembodiment of the invention. The protection NMOS NP1 drain is connectedto the first voltage source, Vcc, and the device source is connected toa second voltage source Vss, typically ground. The protection NMOS NP1gate is connected to the first side of a resistor R1, and the secondside of the resistor R1 is connected to the second voltage source, Vss.The resistor typically has a value of between 1 and 100 K ohms andassures that the protective NMOS device NP1 is in the “off” state duringnormal circuit operation. Another significant aspect of the invention isthat ESD protection NMOS NP1 device has a special diffusion 128 underand around the normal drain diffusion region of opposite dopent than theN+ drain diffusion.

[0036] This special diffusion 128 of opposite dopent to the N+ drain,and therefore of similar dopent to the substrate, but of higherconcentration, reduces the breakdown voltage of the P-N substrate-drainjunction, which also forms the base collector junction of a parasiticNPN bipolar transistor TX1 electrically in parallel with NMOS NP1.During an ESD voltage event on the Vcc bus, a higher than normal voltagewill be placed on Vcc and therefore the drain of NP1 and the collectorof parasitic transistor TX1. TX1 will go into breakdown mode at somepoint preventing the ESD voltage from going higher and providing adischarging means for ESD energy to ground. The reduction indrain-substrate junction breakdown voltage provided by the specialdiffusion region 128, and therefore also the collector base junctionbreakdown voltage, allows current to flow into the substrate P baseregion at a lower voltage than otherwise. This current flow will raisethe base voltage and turn on the parasitic transistor TX1. It must benoted that the special diffusion region 128 is larger than in prior art,extending under and around the full NP1 drain diffusion region.

[0037] When the ESD voltage is removed, the protection NMOS NP1 willreturn to its normal off state as assured by the gate being connected toground through the resistor R1. This off state draws no power from thedevice power bus, and prevents the protection device from interferingwith normal circuit operation.

[0038]FIG. 2B shows a representative cross section of the Vcc to Vsspower ESD protection device NP1 with special drain diffusion. A P dopedsubstrate of between 1E14 to 1E15 atoms per cubic centimeter (a/cm³) ispatterned by convention means such as using photoresist in conjunctionwith other suitable masks such as silicon nitride SiN) to define activecircuit areas. Thick field oxide (FOX) 112 is thermally grown withprocess temperatures typically between 700 and 1200 degrees centigradeto a thickness between 4000 and 10000 angstroms (521 ).

[0039] A gate oxide insulation layer is formed by the thermal growth ofthe silicon substrate as is well known in the art, to a thickness ofbetween 70 and 350 Å. A gate conduction layer 116 is depositedconformally, typically polysilicon (poly) or polycide to a thickness ofbetween 1500 and 4500 Å. The gate poly conduction layer 16 is typicallydoped with an donor element such as phosphorous (P) to a resultantconcentration of 1E18 to 1E21 a/cm³ to improve conductivity. The gatelayer is then patterned by conventional lithography followed by etchingto form the gate structure 115 consisting of gate oxide 114 and gateconductor element 116.

[0040] A first ion implant using the gate structure 115 as a mask isperformed using phosphorous P31 at a concentration between 1E13 and 1E14a/cm². This forms the N− regions 126 known as lightly doped drainextensions (LDD) with typical dopent density of between 1E16 and 1E18a/cm³. A conformal insulating layer of SiO₂ or other suitable insulatorsuch as SiN is deposited over the entire surface by chemical vapordeposition (CVD) to a thickness of between 1000 and 3000 Å. The layer ispatterned and etched by an anisotropic reactive ion etch to form spacers118 on the sides of the device gate 115.

[0041] A heavy ion implant is now performed, using arsenic AS75 at adosage of between about 1E15 and 1E16 a/cm². A drive in step istypically performed at a temperature of between 750 and 950 degreescentigrade for between 10 and 60 minutes. This results the heavily dopedsource region 122 and drain region 124 with a resultant dopentconcentration of between 1E19 and 1E12 a/cm³.

[0042] A key step to the invention is now performed. The device ispatterned with conventional lithography to mask all areas except thedevice drain 124. An implant using an acceptor dopent such as boron B11with a dosage concentration of between 1E3 and 1E14 a/cm² and an implantenergy of between 10 and 80 KeV, This results in an imbedded dopedregion 128 under the drain region 124 with a typical dopent density ofbetween 1E16 and 1E19 a/cm³. This feature reduces the junction breakdowncharacteristic of the Vcc to Vss power ESD protection device NP1 greatlyenhancing the protection capability.

[0043] An insulating layer 120 of SiO₂ or BPSG other suitable insulatingmaterial is now formed over the entire structure to a thickness between2000 and 8000 Å. The layer is patterned by conventional photolithographyand etched to form contact openings to the substrate surface for thesource region 122 and drain region 124.

[0044] Device processing is continued to completion. This includes ablanket metal evaporation to form the electrical conductor system.Patterning and etching to form the source 122 and drain 124 electricalconductors follow the blanket evaporation. The drain conductor isconnected to the first voltage source, Vcc. The drain electricalconductor is connected to the second voltage source, Vss.

[0045] The gate conductor element can be a metal system of aluminum ordoped aluminum, or a doped polysilicon conductor element.

[0046] The gate conductor is connected to one side of a diffusedresistor which has a value between 1000 and 100,000 ohms. The other sideof the resistor is connected to the second voltage source, Vss orground.

[0047] The improvements provided by this unique protection devicecircuit under ESD testing are shown in Table 1. The ESD test voltage asrepresented by the Human Body Model (HBM)—shows a nominal 3.5 timesimprovement for the invention device over a conventional previous artdesign. TABLE 1 Test Result for Conventional vs. Special Diffused Busprotection Device Device Level HBM Conventional Protected Bus I/O 600 VSpecial Diffused NMOS Bus protected I/O 2.1 KV

[0048] The method for creating the improved Vcc to Vss power protectiondevice is illustrated in FIG. 3. As shown in element 40 of the flowdiagram, connecting the source of the used PMOS device and the sourceand gate of the unused PMOS to the first voltage source, typically Vcc,can initiate the method. It is continued as indicated in FIG. 3 element42 by connecting the drains of the used and unused PMOS devices to thestacked NMOS input/output pad. Continue as indicated in element 44 byconnecting the drain of the used PMOS device to the drain of a firstused NMOS device, and connecting the drain of the unused PMOS device tothe drain of a first unused NMOS device. Element 46 indicates theconnecting of the gate of the used PMOS device and the gate of thesecond used NMOS device to separate internal circuit logic signal linescontinues the method.

[0049] Element 48 shows the connecting of the gates of the first usedand unused NMOS devices to a first voltage source, Vss. Element 50continues the process by connecting the source of the first used NMOS tothe drain of the second used NMOS and connecting the source of the firstunused NMOS device to the drain of the second unused NMOS device.Element 52 depicts connecting the source of the second used NMOS and thesource and the gate of the second unused NMOS device to a second voltagesource, typically ground.

[0050] The ESD protection capability is provided as shown in FIG. 3element 54 by creating an ESD protection NMOS device with a specialdiffusion region under and around the NMOS normal drain region and ofopposite dopent than the N+ drain region. The dopent region is typicallycreated by suitably patterning the device with a masking element such asphotoresist that covers the device except for the exposed drain area.Then an implant is performed typically using a boron ion implant sourcewith a dopent concentration of between 1E13 and 1E14 a/cm² and animplant energy of between 10 and 80 KeV to produce a P− region ofbetween E16 and E19 a/cm³. Continuing as indicated in element 56 byconnecting the drain of the ESD protection NMOS device to the firstvoltage source, Vcc, and the drain to a second voltage source, Vss orground. The method continues in element 58 by connecting the gate of theESD protection NMOS device to the first side of a resistor and completedas indicated in element 60 by connecting the second side of the resistorto the second voltage source Vss.

[0051] While the invention has been particularly shown and describedwith reference to the preferred embodiments thereof, it will beunderstood by those skilled in the art that various changes in form anddetails may be made without departing from the spirit and scope of theinvention.

What is claimed is:
 1. A protection circuit for protecting integratedsemiconductor active devices from damage due to ESD voltages appearingon the circuit power bus lines said circuit comprising: at least oneswitching circuit string composed of a first and second used NMOS deviceand a used PMOS device , wherein the gate of said first used NMOS deviceis connected to a first voltage source and the drain element of saidfirst used NMOS device is connected to said active devices input/outputsignal pad and to the drain element of said used PMOS device, and thesource of said first used NMOS device is connected to the drain elementof said second used NMOS device and the gates of said second used NMOSand said used PMOS are connected to an internal circuit and the sourceof said used second NMOS is connected to a second voltage source, andthe source of said used PMOS is connected to a first voltage source; anda protection discharging means for discharging ESD energy appearingbetween said first and said second voltage source.
 2. The circuitaccording to claim 1 wherein said protection discharging means comprisesa discharging NMOS device with a first and a special second draindiffusion, and a resistor.
 3. The circuit according to claim 2 whereinthe drain of said discharging NMOS device is connected to said firstvoltage source, and the source of said discharging NMOS device isconnected to said second voltage source.
 4. The circuit according toclaim 2 wherein the gate of said discharging NMOS device is connected tothe first end of said resistor and the second end of said resistor isconnected to said second voltage source.
 5. The circuit according toclaim 2 wherein said first drain diffusion is a N+ donor diffusion toform a normal NMOS drain region.
 6. The circuit according to claim 2wherein said special second drain diffusion is of opposite dopent thansaid first drain diffusion and extends under and around said normaldrain region.
 7. The circuit according to claim 2 wherein said resistorhas a value between 1 and 100 K ohms.
 8. The circuit according to claim1 wherein said switching circuit string provides a driving current tosaid output pad.
 9. The circuit according to claim 1 wherein a value ofsaid driving current is determined by the total number of said switchingstrings and whereby each said string can supply a current between 2 and48 ma.
 10. The circuit according to claim 1 wherein said first voltagesource is between 2.5 and 5 volts.
 11. The circuit according to claim 1wherein said second voltage source is ground.
 12. An effective Vcc toVss power ESD protection device with reduced junction breakdown voltageconnected between Vcc and Vss power bus lines comprising: a siliconsubstrate having a first dopent type; field oxide regions within saidsubstrate for isolation of said ESD protection device; a FET gate withabutting spacers for said ESD protection device; multiple regions of asecond dopent type of opposite dopent to said substrate for said ESDprotection device between said gate and said field oxide regions;multiple regions of a third dopent type of opposite dopent to saidsubstrate for said ESD protection device between said gate and saidfield oxide regions; A special fourth dopent region of similar dopent tosaid substrate beneath one said second and third dopent region; aprotective insulation layer over said ESD protection device; and first,second and third electrical conductor elements.
 13. The ESD protectiondevice of claim 12 wherein said substrate is of P dopent with aconcentration between 1E14 and 1E15 a/cm³.
 14. The ESD protection deviceof claim 12 wherein said field oxide isolation regions are thermallygrown to a thickness of between 4000 and 10,000 Å.
 15. The ESDprotection device of claim 12 wherein said FET gate consists of gateoxide insulator between 70 and 350 Å in thickness and a polysiliconconduction element between 1500 and 4500 Å in thickness.
 16. The ESDprotection device of claim 12 wherein said FET gate abutting spacers areof silicon oxide or silicon nitride.
 17. The ESD protection device ofclaim 12 wherein said multiple regions of second dopent type are N dopedto a dopent concentration of between 1E16 and 1E18 a/cm³.
 18. The ESDprotection device of claim 12 wherein said multiple regions of a thirddopent type are of N dopent with a dopent concentration of between 1E19and 1E21 a/cm³ and form the source and drain regions of a NMOS FET. 19.The ESD protection device of claim 12 wherein said special fourth dopentregion is doped with a P dopent with a dopent concentration of between1E16 and 1E19 a/cm³ and is located below and partially surrounding saidNFET drain region.
 20. The ESD protection device of claim 12 whereinsaid drain electrical conductor element is connected to a first voltagesource Vcc, and said source electrical conductor element is connected toa second voltage source, Vss or ground. resistor.
 21. The ESD protectiondevice of claim 12 wherein said gate electrical conductor element isconnected to the first end of a diffused resistor with a value between1000 and 100000 ohms.
 22. The ESD protection device of claim 12 whereinthe second end of said resistor is connected to said second voltagesource Vss, or ground.
 23. A method of forming a protection circuit forprotecting integrated semiconductor active devices from damage due toESD voltages appearing on the circuit power bus lines said methodcomprising: connecting source region of a used PMOS device and thesource and gate of an unused PMOS device to a first voltage source;connecting the drains of said used and unused PMOS devices to saidactive devices input/output pad; connecting the drain of said used PMOSdevice to a drain of a first used NMOS device, and the drain of saidunused PMOS device to a drain of a first unused NMOS device; connectingthe gate of said used PMOS device and the gate of a second used NMOSdevice to separate logic signal lines; connecting the gates of saidfirst used and said first unused NMOS devices to said first voltagesource; connecting the source of said first used NMOS device to thedrain of said second used NMOS device and connecting the source of saidfirst unused NMOS device to the drain of a second unused NMOS device;connecting the source of said second used NMOS and the source and gateof said second unused NMOS device to a second voltage source; andconnecting said ESD protection discharging means for discharging ESDenergy appearing between said first and second voltage source.
 24. Themethod according to claim 23 wherein said ESD protection dischargingmeans comprises a discharging NMOS device with a special diffusionregion under and around said device normal drain region of oppositedopent than said normal drain region, and a resistor with a valuebetween 1000 and 100,000 ohms.
 25. The method according to claim 24wherein said ESD protection discharging means is connected to thecircuits to be protected by connecting said drain of said dischargingNMOS device to said first voltage source and connecting the source ofsaid discharging NMOS to said second voltage source.
 26. The methodaccording to claim 24 wherein said ESD protection discharging means isconnected to the circuits to be protected by connecting the gate of saiddischarging NMOS device to the first end of said resistor and connectingthe second end of said resistor to said second voltage source.
 27. Themethod according to claim 24 wherein said special diffusion region underand around said discharging NMOS device normal drain region is createdby an ion implant of boron with a dosage between 1E13 and 1E14 a/cm² andan energy of between 10 and 80 KeV, to produce a resultant dopentconcentration of between 1E 16 and 1E19 a/cm³.
 28. The method accordingto claim 23 whereby said first voltage source is generated to a positivelevel above ground designated Vcc with a value between 2.5 and 5 volts.29. The method according to claim 23 whereby said second voltage sourcedesignated Vss is connected to a voltage level below Vcc, typicallyground.
 30. The method according to claim 23 whereby said separate logicsignal lines are connected to internal logic devices.